1) Field of the Invention
The present invention relates to a quasi-synchronous detection and demodulation circuit for demodulating a quadrature amplitude modulation (QAM) signal, and more particularly to a quasi-synchronous detection and demodulation circuit having a contingent demodulation carrier phase removing function and a frequency discriminator used for the same and for detecting the difference between the carrier wave frequency of a modulating wave and a reference carrier wave frequency for demodulation.
2) Description of the Related Art
In the quasi-synchronous detection and demodulation system, when a quadrature modulated wave is demodulated, a demodulation signal can be obtained by a phase rotation process where a signal demodulated with a local signal of a fixed frequency is subjected to a digital carrier reproduction (DCR).
(a) Explanation of synchronous detection and demodulation system. PA0 (b) Explanation of quasi-synchronous detection and demodulation system. PA0 (c) Explanation of phase contingent. PA0 (d) Explanation of frequency discriminator.
First, an explanation will be made below as for a synchronous detection and demodulation system.
FIG. 17 shows a conventional demodulation circuit and its synchronous detection operation. Referring to FIG. 17, numeral 11 represents a hybrid (H), 12 and 13 represent a detecting circuit, respectively, 14 represents a voltage controlled oscillator (VCO), 15 represents a 90-degree hybrid (H), 16 and 17 represent a low pass filter, respectively, 18 and 19 represent a variable gain amplifier, 20 and 21 each represents an adder, respectively, 22 and 23 each represents an analog to digital converter (A/D converter), respectively, 24 represents an equalizer, 25 represents a control unit (CONT), and 26, 27, 28, 29, and 30 each represents a low pass filter, respectively.
In the synchronous detection and demodulation system, the intermediate frequency signal (IF IN) subjected to a quadrature modulation (QAM) is branched in two by the hybrid 11 to input respectively to one inputs of the detecting circuits 12 and 13. The voltage controlled oscillator 14 forms a carrier reproducing circuit (CR) and reproduces a clock synchronized with an input signal. The 90-degree hybrid 15 shifts the local signal by 90.degree. and applies it to the other inputs of the detecting means 12 and 13. The detecting circuit 12 produces an I-channel demodulation output and the detecting circuit 13 produces a Q-channel demodulation output.
The I-channel demodulation output is subjected to a band limit in the low pass filter 16 and then to an automatic gain control (AGC) of a signal amplitude in the variable gain amplifier 18. The Q-channel demodulation output is subjected to a band limit in the low pass filter 17 and then to an automatic gain control (AGC) of a signal amplitude in the variable gain amplifier 19. Furthermore, the I-channel output is subjected to a drift control (DRC) in the adder 20 to compensate the shift of a direct current component and converted into, for example, an 8-bit digital signal by the A/D converter 22. The Q-channel output is subjected to a drift control (DRC) in the adder 21 to compensate the shift of a direct current component and converted into, for example, an S-bit digital signal by the A/D converter 23. The equalizer 24 such as a transversal equalizer or the similar circuits performs an desired amplitude equalization of the two signals and produces the output data Ich and Qch.
The control unit 25 produces frequency control signals for the VCO 14 from the demodulated data Ich and Qch. In the control signals, when the first bit of the demodulated data indicates a polarity signal (D), bits in a predetermined number less than the second bit thereof indicate an effective data, and the 1-bit less than the effective data indicates an error signal (E), the exclusive-OR of D.sub.(I) and E.sub.(Q) or the exclusive-OR of D.sub.(Q) and E.sub.(I) are used as data where the I-channel data and the Q-channel signal are respectively represented with a subscript I and a subscript Q. For example, in the 16 QAM system, the second and third bits represent an effective data and the fourth bit represents an error signal. The signal is smoothed by the low pass filter 26 and then is sent as a control voltage to the VCO 14. The VCO 14 varies its oscillation frequency and is controlled so as to synchronize with the frequency of the input signal.
The control unit 25 produces an AGC control signal from demodulation data Ich and Qch. In this case, an exclusive-OR data of D.sub.(I) and E.sub.(I) is used as a control signal for the I-channel. An exclusive-OR data of D.sub.(Q) and E.sub.(Q) is used as a control signal for the Q-channel. These signals are respectively supplied to the variable gain amplifiers 18 and 19 via the low pass filters 27 and 28 to perform a base band (B,B) AGC controlling the amplitude of the demodulation signal of each Of the channels.
Furthermore, the control unit 25 produces DRC control signals from the demodulation data I.sub.CH and Q.sub.CH. E.sub.(I) data is used as a control signal for the I-channel and E.sub.(Q) data is used as a control signal for the Q-channel. One control signal is smoothed by the low pass filters 29 and supplied to the adder 20 to compensate the direct current component of the demodulation data in the I-channel. The other control signal is smoothed by the low pass filters 30 and supplied to the adder 21 to compensate the direct current component of the demodulation data in the Q-channel.
FIG. 18 shows a quasi-synchronous detection and demodulation circuit having the configuration that a fixed frequency oscillator, a phase rotation unit, and a digital variable frequency oscillator are added to the synchronous detection and demodulation in FIG. 17, but the carrier reproduction unit thereof is omitted. In FIG. 18, like numerals represent the similar elements to those in FIG. 17. Numeral 31 represents a fixed frequency oscillator (OSC), 32 represents a phase rotation unit, and 33 represents a low pass filter, and 34 represents a digital variable frequency oscillator (DVCO).
FIG. 19 shows the configuration of the phase rotation unit 32. Numerals 36, 37, 38, and 39 are a mixer, respectively, and 40 and 41 are an adder, respectively. In FIG. 19, it is assumed that when I and Q represent the signals before a phase rotating process and I' and Q' represent the signals after the phase rotating process, a phase rotation to be desired is .circle-w/dot.. By inputs of cosine(.theta.), sine(.theta.), sine(.theta.), and cosine(.theta.) signals to the mixers 36, 37, 38, and 39, respectively, a desired phase rotation .theta. can be obtained by the following expressions: EQU I'=I cosine(.theta.)-Q sine(.theta.) (1) EQU Q'=I sine(.theta.)+Q cosine(.theta.) (2)
FIG. 20 shows the configuration of the DVCO 34. Numerals 43 and 44 represent each a delay circuit, respectively, 45 represents an adder, and 46 and 47 are a read-only memory (ROM), respectively.
The control unit 25, like that shown in FIG. 17, produces a frequency control signal from the demodulation data I.sub.CH and Q.sub.CH. The control signal is smoothed by the low pass filter 33 and then is added to the delay circuit 43 to hold for a predetermined space of time, Then the accumulator (integrator VCO) formed of a delay circuit 44 and an adder 45 counts up or down the delayed control signal every sampling period and adds the output as an address to the ROMs 46 and 47. The address corresponds to the phase angle .theta. in the phase rotation unit 32. The ROMs 46 and 47 output the sine (.theta.) end cosine(.theta.) data corresponding to the address, respectively.
FIG. 21 shows a rough configuration on the modulation side. Numerals 48 and 49 represent each a digital to analog converter (D/A converter), respectively, 50 and 51 represent a low pass filter, respectively, 52 and 53 represent each a mixer, respectively, 54 represents a hybrid, 55 represents a carrier oscillator (OSC), and 56 represents a 90-degree hybrid.
In the above circuit structure, the I-channel input signal is converted to an analog signal from a digital signal by means of the D/A converter 48, band-limited by the low pass filter 50, and then inputs to the mixer 52 while the Q-channel input signal is converted to an analog signal from a digital signal by means of the D/A converter 49, band-limited by the low pass filter 51, and then inputs to the mixer 53. Since the 90-degree hybrid 56 supplies in an quadrature phase a local signal with a constant frequency of the OSC 55 to the other inputs of the mixers 52 and 53, the hybrid 54 synthesizes the outputs from the mixers 52 and 53 to produce a quadrature modulation wave.
Generally, in order to transmit the digital signal to a distant place, the carrier modulating and transmitting method has been utilized. Moreover, since the frequency band where digital signals are transmitted can be used effectively, the QAM modulation system has been widely used as described above. The demodulation of the QAM signal requires adding a carrier synchronized with the carrier of the received QAM signal so that a carrier reproducing circuit is used to reproduce the carrier.
The carrier of the received QAM signal includes four kinds of phases of 0, .pi./2, .pi., and 3.pi./2. However, since it cannot be decided what kind of a phase a received QAM signal has, a carrier reproducing circuit for the QAM signal reproduces a carrier which synchronizes with one of the four kinds of phases.
When the difference between the phase of a carrier reproduced by the carrier reproducing circuit and the phase of a carrier of the received QAM signal is zero, the demodulation digital signal coincides with the original input digital signal. However, when there is a phase difference, the input does not coincide with the digital signal of the demodulation output. For that reason, a signal which is obtained by executing a differential logic with a signal preceding by one symbol of the transmitted input signal is transmitted and an original digital signal which is obtained by executing a differential releasing logic with a signal preceding by one symbol of the demodulated output signal is obtained.
As described above, the QAM digital signal is transmitted by subjecting an input digital signal to a differential logical operation. Hence, a logic circuit for performing the complicated differential logical and differential releasing operation is required. When the QAM modulated digital signal is transmitted after its differential logical operation, one-bit error of the transmitted signal appears as two-bit error at the differential logical releasing operation, whereby the bit error rate becomes worse,
As described above, in the recent digital radio transmission system, a multi-level transmission system employing a quadrature amplitude modulation has been widely used since having advantages in an effective use of radio frequency and others. In such a modulation system, the number of the multi-level is increasing with an increasing transmission capacity and a request for the improved performance. The increasing multi-level number requires a higher accuracy of the signal layout on a modulation wave signal space diagram (hereinafter merely abbreviated to "signal space"). The lower accuracy may lead to, for example, drift, pseudo absorption, or other troubles at the demodulation time.
In order avoid such troubles and to obtain a stable transmission system, it is necessary to perform a transmission distortion compensation, a drift compensation of a discrimination circuit, fading equalizing, interference noise compensation, and other techniques. These techniques can be realized when the frequency of a reference carrier signal used for a demodulation operation coincides in higher accuracy with the carrier frequency of a modulation wave (received wave). Generally, the receiving device includes an automatic frequency control circuit which controls sequentially and variably the frequency of a reference carrier signal to a proper value to absorb the difference within a fixed accuracy. The automatic frequency control circuit includes a frequency discriminator for providing the above control criteria.
FIG. 22 is a diagram showing a constructional example of a conventional frequency discriminator of this kind. In the figure, the quadrature detector 150 receives a receiving signal converted with a predetermined intermediate frequency and produces two quadrature base band signals I and Q to input to the A/D converters 22 and 23, respectively. The output of the A/D converter 22 is separated in two to connect to the multiplicand inputs of the multipliers 152-1 and 152-2. The output of the A/D converter 23 is separated in two to connect to the multiplicand inputs of the multipliers 152-1 and 152-2. The output of the multiplier 152-1 is connected to the minuend inputs of the subtractor 153. The output of the multiplier 152-2 is connected to the subtrahend inputs of the subtractor 153. The output of the subtractor 153 is connected to the input of the latch circuit (FF) 154 and the subtrahend input of the subtractor 155. The output of the latch circuit 154 is connected to the minuend input of the subtractor 155. The output of the subtractor 155 is connected to the control input of an automatic frequency control circuit (AFC) by way of the integrator 156 arranged at the rear stage.
In the frequency discriminator structure, the receiving signal is subjected to a 4-phase PSK modulation in accordance with transmitted information. As shown in FIG. 23, on the time axis calibrated by clocks synchronized with each bit of the transmission information, it is assumed that a demodulated signal (hereinafter referred to "symbol") of a received wave at the time t.sub.n is at the signal point r.sub.n shown by the coordinate (i(t.sub.n),q(t.sub.n)) in the signal space and the normal position of the signal point is at the signal point R1 shown by the coordinates (i.sub.0 (t.sub.n),q.sub.0 (t)) in the signal space. Generally, with respect to the polarities i.sub.d (t.sub.n) and q.sub.d (i.sub.n) corresponding to the axes I and Q in an error signal space shown in the difference between the coordinates, the phase difference .DELTA..circle-w/dot.(tn) between the a received signal and a reference carrier signal used at a demodulation time is held by the following expression: EQU .DELTA..circle-w/dot.(tn).apprxeq..sub.d (t.sub.n).times.(q(t.sub.n)-q.sub.0 (t.sub.n))-(i(t.sub.n)-i.sub.0 (t.sub.n)).times.q.sub.d (t.sub.n).apprxeq.i.sub.d (t.sub.n).times.q.sub.e (t.sub.n)-i.sub.e (t.sub.n).times.q.sub.d (t.sub.n) (1-1)
Furthermore, with respect to the time t.sub.n-1 defined on the basis of the clock preceding by the time t.sub.n on the time axis, the frequency component .DELTA.f of the error is held by the following expression: EQU .DELTA.f(t.sub.n)=.DELTA..circle-w/dot.(t.sub.n)-.DELTA..circle-w/dot.(t.su b.n-1) (1-2)
The multiplier 152-1 calculates every clock period the value of the first term of the right member of the expression (1-1) by using the each symbol digital-converted by the A/D converters 22 and 23. In the similar manner, the multiplier 152-2 calculates the value of the second term of the right member of the expression (1-1). The subtractor 153 produces the phase difference .DELTA..circle-w/dot. shown by the expression (1-1) from the above terms. The subtractor 155 produces the frequency component .DELTA.f shown by the expression (1-2) obtained by taking the difference between the preceding phase difference .DELTA..circle-w/dot.(t.sub.n-1) stored in the memory circuit 154 and the phase difference from the subtractor 153. The integrator 156 is formed of a counter or an accumulator. The frequency component obtained thus integrates the average value of a frequency deviation of a reference carrier wave from demodulation with respect to the carrier frequency of the received signal to send it to the automatic frequency control circuit.
In the conventional frequency discriminator, as shown in FIG. 24, when the signal point ((it.sub.1), q(t.sub.1)) of the symbol obtained by demodulating the received signal at the time t.sub.1 is positioned by way of the axis Q so as to oppose to the signal point (i(t.sub.2),q(t.sub.2)) of the symbol obtained by demodulating the received signal at the following time t.sub.2, the phase differences at these times are expressed by the following inequalities: EQU .DELTA..circle-w/dot.(t.sub.1)&gt;0 EQU .DELTA..circle-w/dot.(t.sub.2)&lt;0
The above inequalities has a different sign to each other. The frequency component obtained from the phase differences is held by the following expression: EQU .DELTA.f(t.sub.2)=.DELTA..circle-w/dot.(t.sub.2)-.DELTA..circle-w/dot.(t.su b.1)&lt;0
As shown by the above expression, since the sign represents a reversed value, a large error occurs in the frequency deviation of a reference carrier wave to be obtained. Furthermore, the error occurs on the I axis in the signal space. Without being limited to the 4-phase PSK modulation system, the error occurs in the quadrature modulation system having a large number of multi-levels such as 16QAM.
In the multi-level quadrature amplitude modulation system such as 16QAM modulation, since a change in the amplitude component of a received signal according to a transmission information varies the direct distance from the origin of the signal space to a signal point corresponding to the signal, an error in the phase difference calculated by the expression (1-1) occurs, thus resulting in a degraded accuracy to the frequency deviation of a reference carrier wave.